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» Constraint extraction for pseudo-functional scan-based delay...
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VTS
2005
IEEE
96views Hardware» more  VTS 2005»
13 years 10 months ago
Pseudo-Functional Scan-based BIST for Delay Fault
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng
ASPDAC
2005
ACM
107views Hardware» more  ASPDAC 2005»
13 years 7 months ago
Constraint extraction for pseudo-functional scan-based delay testing
Recent research results have shown that the traditional structural testing for delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults t...
Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Chen...
ATS
2003
IEEE
131views Hardware» more  ATS 2003»
13 years 10 months ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
DATE
2010
IEEE
134views Hardware» more  DATE 2010»
13 years 10 months ago
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
Xiao Liu, Yubin Zhang, Feng Yuan, Qiang Xu