20 search results - page 4 / 4 » Correct Passive Testing Algorithms and Complete Fault Covera... |
ICCAD
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
DAC
2003
ACM
13 years 11 months ago
2003
ACM
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
GLVLSI
2003
IEEE
13 years 11 months ago
2003
IEEE
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
DAC
2009
ACM
13 years 10 months ago
2009
ACM
Process scaling has given designers billions of transistors to work with. As feature sizes near the atomic scale, extensive variation and wearout inevitably make margining unecono...
ASC
2011
13 years 18 days ago
2011
A new paradigm for online EH regeneration using Genetic Algorithms (GAs) called Competitive Runtime Reconfiguration (CRR) is developed where performance is assessed based upon a b...