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ATS
1998
IEEE
170views Hardware» more  ATS 1998»
13 years 9 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
TLDI
2003
ACM
135views Formal Methods» more  TLDI 2003»
13 years 10 months ago
Typed compilation of recursive datatypes
Standard ML employs an opaque (or generative) semantics of datatypes, in which every datatype declaration produces a new type that is different from any other type, including othe...
Joseph Vanderwaart, Derek Dreyer, Leaf Petersen, K...
ISCA
2008
IEEE
132views Hardware» more  ISCA 2008»
13 years 11 months ago
Online Estimation of Architectural Vulnerability Factor for Soft Errors
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
13 years 10 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
USENIX
2007
13 years 7 months ago
DiskSeen: Exploiting Disk Layout and Access History to Enhance I/O Prefetch
Current disk prefetch policies in major operating systems track access patterns at the level of the file abstraction. While this is useful for exploiting application-level access...
Xiaoning Ding, Song Jiang, Feng Chen, Kei Davis, X...