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» Datapath Synthesis for Standard-Cell Design
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VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
13 years 11 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran
GLVLSI
2003
IEEE
194views VLSI» more  GLVLSI 2003»
13 years 10 months ago
RF CMOS circuit optimizing procedure and synthesis tool
In this paper, we discuss a methodology to design and synthesize analog CMOS components such as RF amplifiers. The inputs of the synthesis tool are the circuit specifications desc...
Chandrasekar Rajagopal, Karthik Sridhar, Adrian Nu...
ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
13 years 11 months ago
Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
Saraju P. Mohanty, Elias Kougianos, Ramakrishna Ve...
DAC
2004
ACM
13 years 10 months ago
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
DATE
2003
IEEE
138views Hardware» more  DATE 2003»
13 years 10 months ago
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric
There have been several recent attempts to include duplication-based on-line testability in behaviourally synthesized designs. In this paper, on-line testability is considered wit...
Petros Oikonomakos, Mark Zwolinski, Bashir M. Al-H...