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» Debugging of Toffoli networks
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GLVLSI
2007
IEEE
135views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Exact sat-based toffoli network synthesis
Compact realizations of reversible logic functions are of interest in the design of quantum computers. Such reversible functions are realized as a cascade of Toffoli gates. In th...
Daniel Große, Xiaobo Chen, Gerhard W. Dueck,...
ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 1 months ago
Fredkin/Toffoli Templates for Reversible Logic Synthesis
Reversible logic has applications in quantum computing, low power CMOS, nanotechnology, optical computing, and DNA computing. The most common reversible gates are the Toffoli gate...
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
IPSN
2011
Springer
12 years 8 months ago
Demo abstract: Debugging wireless sensor network simulations with YETI and COOJA
Richard Huber, Philipp Sommer, Roger Wattenhofer
DATE
2009
IEEE
116views Hardware» more  DATE 2009»
13 years 11 months ago
A high-level debug environment for communication-centric debug
—A large part of a modern SOC’s debug complexity resides in the interaction between the main system components. ion-level debug moves the abstraction level of the debug process...
Kees Goossens, Bart Vermeulen, Ashkan Beyranvand N...
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
13 years 11 months ago
A multi-core debug platform for NoC-based systems
Network-on-Chip (NoC) is generally regarded as the most promising solution for the future on-chip communication scheme in gigascale integrated circuits. As traditional debug archi...
Shan Tang, Qiang Xu