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DFT
2007
IEEE
104views VLSI» more  DFT 2007»
13 years 11 months ago
Reduction of Fault Latency in Sequential Circuits by using Decomposition
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky
ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
13 years 10 months ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...
EDCC
2005
Springer
13 years 11 months ago
Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs
Abstract. Current paper proposes an efficient alternative for traditional gatelevel fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSB...
Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jut...
DAC
1998
ACM
14 years 6 months ago
Fault-Simulation Based Design Error Diagnosis for Sequential Circuits
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, ...