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» Defect-Aware Design Paradigm for Reconfigurable Architecture...
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ISVLSI
2006
IEEE
149views VLSI» more  ISVLSI 2006»
12 years 3 months ago
Defect-Aware Design Paradigm for Reconfigurable Architectures
With advances in process technology, the feature sizes are decreasing, which leads to higher defect densities. More sophisticated techniques, at increased costs are required to av...
Rahul Jain, Anindita Mukherjee, Kolin Paul
DAC
2004
ACM
12 years 10 months ago
Defect tolerant probabilistic design paradigm for nanotechnologies
Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near horizon. However, the trem...
Margarida F. Jacome, Chen He, Gustavo de Veciana, ...
ARC
2006
Springer
157views Hardware» more  ARC 2006»
12 years 1 months ago
PISC: Polymorphic Instruction Set Computers
We introduce a new paradigm in the computer architecture referred to as Polymorphic Instruction Set Computers (PISC). This new paradigm, in difference to RISC/CISC, introduces hard...
Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Won...
CASES
2001
ACM
12 years 1 months ago
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture
The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs...
Girish Venkataramani, Walid A. Najjar, Fadi J. Kur...
FCCM
2004
IEEE
136views VLSI» more  FCCM 2004»
12 years 1 months ago
The MOLEN Processor Prototype
We present a prototype design of the MOLEN polymorphic processor, a CCM based on the co-processor architectural paradigm. The Xilinx Virtex II Pro technology is used as a prototyp...
Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassi...
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