18 search results - page 3 / 4 » Delay Evaluation of High Speed Data-Path Circuits Based on T... |
GLVLSI
2007
IEEE
14 years 2 days ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensate...
ICCAD
2008
IEEE
14 years 2 months ago
2008
IEEE
—To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nanoelect...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
TCAD
2008
13 years 5 months ago
2008
Abstract--The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) deco...