Novel architectures for efficient (m, n) parallel counters

Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3), (15, 4) and (31,5) counters capable of operating at ultra-low voltages are presented. Based on these counters, a generalized architecture is derived for large (m, n) parallel counters. The proposed architecture lays emphasis on the use of multiplexers and a combination of CMOS and transmission gate logic in arithmetic circuits that result in high speed and efficient design. The proposed counter designs have been compared with existing designs and are shown to achieve an improvement of about 45% in delay and a reduction of about 25% in power consumption. Categories and Subject Descriptors B.7.0 Hardware, INTEGRATED CIRCUITS, General General Terms: Design

• Type: Conference
• Year: 2007
• Where: GLVLSI
• Authors: Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas
• Keywords: Architecture, Arithmetic Circuits, GLVLSI 2007, Parallel Counters, VLSI