31 search results - page 2 / 7 » Delay Test Quality Evaluation Using Bounded Gate Delays |
ICC
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract ⎯ Currently, the most advanced framework for stochastic network calculus is the min-plus algebra, providing bounds for the end-to-end delay in networks. The bounds calcu...
ICCAD
2003
IEEE
13 years 10 months ago
2003
IEEE
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
VTS
1996
IEEE
13 years 9 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimen...