138 search results - page 3 / 28 » Delay modeling and static timing analysis for MTCMOS circuit... |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
A technique based on the sensitivity of the output to input waveform is presented for accurate propagation of delay information through a gate for the purpose of static timing ana...
TCAD
2010
13 years 3 months ago
2010
—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
ICCAD
2000
IEEE
13 years 8 months ago
2000
IEEE
ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is dif...