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» Delay modelling improvement for low voltage applications
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ATS
2005
IEEE
144views Hardware» more  ATS 2005»
13 years 10 months ago
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
—Test application at reduced power supply voltage (low-voltage testing) or reduced temperature (low-temperature testing) can improve the defect coverage of a test set, particular...
Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Bec...
GLVLSI
2003
IEEE
239views VLSI» more  GLVLSI 2003»
13 years 10 months ago
CMOS flash analog-to-digital converter for high speed and low voltage applications
A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flas...
Jincheol Yoo, Kyusun Choi, Jahan Ghaznavi
ISCAS
2003
IEEE
279views Hardware» more  ISCAS 2003»
13 years 10 months ago
A high speed low input current low voltage CMOS current comparator
A new high speed low input current comparator is proposed in this paper. Based on a simple negative feedback scheme around the transimpedance stage with an emphasis on a very larg...
K. Moolpho, Jitkasem Ngarmnil, S. Sitjongsataporn
ETS
2006
IEEE
129views Hardware» more  ETS 2006»
13 years 10 months ago
Dynamic Voltage Scaling Aware Delay Fault Testing
The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faul...
Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M....
AIA
2007
13 years 6 months ago
Minimizing leakage: What if every gate could have its individual threshold voltage?
Designers aim at fast but low-power consuming integrated circuits. Since high processing speed always comes with high energy demands, the literature provides several ways to reduc...
Ralf Salomon, Frank Sill, Dirk Timmermann