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» Delay modelling improvement for low voltage applications
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VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
14 years 3 hour ago
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors
The 3-2, 4-2 and 5-2 compressors are the basic components in many applications, in particular partial product summation in multipliers. In this paper novel architectures and desig...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...
DAC
2006
ACM
14 years 6 months ago
Statistical logic cell delay analysis using a current-based model
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
Hanif Fatemi, Shahin Nazarian, Massoud Pedram
IOLTS
2005
IEEE
141views Hardware» more  IOLTS 2005»
13 years 11 months ago
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
13 years 11 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
VLSID
2005
IEEE
170views VLSI» more  VLSID 2005»
13 years 11 months ago
A High-Efficiency, Dual-Mode, Dynamic, Buck-Boost Power Supply IC for Portable Applications
Abstract—Integrated power supplies are critical building blocks in stateof-the-art portable applications, where they efficiently and accurately transform a battery supply into va...
Biranchinath Sahu, Gabriel A. Rincón-Mora