86 search results - page 2 / 18 » Delay-Reduced Combinational Logic Synthesis using Multiplexe... |
DAC
2012
ACM
11 years 7 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...
DAC
2000
ACM
13 years 9 months ago
2000
ACM
In many modern designs, timing is either a key optimization goal and/or a mandatory constraint. We propose the first intellectual property protection technique using watermarking ...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inve...
ARVLSI
1995
IEEE
13 years 8 months ago
1995
IEEE
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...