90 search results - page 1 / 18 » Design, Implementation, and Validation of a New Class of Int... |
MEMOCODE
2007
IEEE
13 years 11 months ago
2007
IEEE
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
TCAD
2008
13 years 4 months ago
2008
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
VLSI
2010
Springer
13 years 3 months ago
2010
Springer
—Latency insensitivity is a promising design paradigm in the nanometer era since it has potential benefits of increased modularity and robustness to variations. Synchronous elas...
ENTCS
2008
13 years 4 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...
JUCS
2007
13 years 4 months ago
2007
: It is a difficult problem that using cellular neural network to make up of analog signal processing circuit. This paper presented the architecture of new cellular neural network ...