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HPCA
2005
IEEE
13 years 11 months ago
Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems
As microprocessors become increasingly interconnected, the power consumed by the interconnection network can no longer be ignored. Moreover, with demand for link bandwidth increas...
Xuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Yue-Kai H...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
13 years 11 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
DAC
2000
ACM
14 years 6 months ago
Hierarchical analysis of power distribution networks
Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, T...
DAC
1996
ACM
13 years 9 months ago
Sizing of Clock Distribution Networks for High Performance CPU Chips
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a c...
Madhav P. Desai, Radenko Cvijetic, James Jensen
ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
14 years 6 days ago
Incremental and on-demand random walk for iterative power distribution network analysis
— Power distribution networks (PDNs) are designed and analyzed iteratively. Random walk is among the most efficient methods for PDN analysis. We develop in this paper an increme...
Yiyu Shi, Wei Yao, Jinjun Xiong, Lei He