38 search results - page 2 / 8 » Design and Management of 3D Chip Multiprocessors Using Netwo... |
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
DAC
2006
ACM
13 years 7 months ago
2006
ACM
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
DATE
2009
IEEE
14 years 1 days ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
Designers are moving toward chip-multiprocessors (CMPs) to leverage application parallelism for higher performance while keeping design complexity under control. However, to date,...
HIPEAC
2009
Springer
13 years 9 months ago
2009
Springer
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient sh...