- Designing a power-gating structure with high performance in the active mode and low leakage and short wakeup time during standby mode is an important and challenging task. This p...
In this paper, we propose a new hetero-material stepped gate (HSG) SOI LDMOS in which the gate is divided into three sections - an n+ gate sandwiched between two p+ gates and the ...
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. As technology scales to deep sub-...
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...
Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel