427 search results - page 1 / 86 » Design and application of multimodal power gating structures |
ISQED
2009
IEEE
13 years 11 months ago
2009
IEEE
- Designing a power-gating structure with high performance in the active mode and low leakage and short wakeup time during standby mode is an important and challenging task. This p...
VLSID
2010
IEEE
13 years 8 months ago
2010
IEEE
In this paper, we propose a new hetero-material stepped gate (HSG) SOI LDMOS in which the gate is divided into three sections - an n+ gate sandwiched between two p+ gates and the ...
IOLTS
2008
IEEE
13 years 11 months ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
CSREAESA
2006
13 years 6 months ago
2006
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. As technology scales to deep sub-...
ISLPED
2003
ACM
13 years 9 months ago
2003
ACM
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...