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ISLPED
1999
ACM
131views Hardware» more  ISLPED 1999»
13 years 9 months ago
Challenges in clockgating for a low power ASIC methodology
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
David Garrett, Mircea R. Stan, Alvar Dean
ICCD
2005
IEEE
121views Hardware» more  ICCD 2005»
14 years 2 months ago
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem...
Bradley R. Quinton, Mark R. Greenstreet, Steven J....
ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
13 years 9 months ago
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications
- The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low ...
Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan
HPCC
2007
Springer
13 years 11 months ago
A Low-Power Globally Synchronous Locally Asynchronous FFT Processor
Abstract. Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to efï¬...
Yong Li, Zhiying Wang, Jian Ruan, Kui Dai