88 search results - page 2 / 18 » Design for manufacturability in submicron domain |
VTS
2000
IEEE
13 years 9 months ago
2000
IEEE
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
ion. Production use of text-based methodology has enabled designers to capture designs of hundreds of thousands of gates using graphic ESDA tools. Source: Data Quest (Verilog/VHDL ...
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
Ultra-deep submicron manufacturability impacts physical design (PD) through complex layout rules and large guardbands for process variability; this creates new requirements for ne...
DAC
2006
ACM
13 years 11 months ago
2006
ACM
Silicon design implementation has become increasingly complex with the deep submicron technologies such as 90nm and below. It is common to see multiple processor cores, several ty...
DAC
1999
ACM
14 years 6 months ago
1999
ACM
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminate...