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DAC
1996
ACM
13 years 9 months ago
Power Estimation of Cell-Based CMOS Circuits
PPP is a Web-based simulation and synthesis environment for low-power design. In this paper we describe the gate-level simulation engine of PPP, that achieves accuracy always with...
Alessandro Bogliolo, Luca Benini, Bruno Ricc&ograv...
ISCAS
2006
IEEE
105views Hardware» more  ISCAS 2006»
13 years 11 months ago
A new Spice-oriented frequency-domain optimization technique
— There are many kinds of optimization techniques for designing high-performance RF circuits. In this paper, we propose a new frequency-domain Spice-oriented optimization algorit...
Masayoshi Oda, Yoshihiro Yamagami, Yoshifumi Nishi...
DAC
2000
ACM
14 years 6 months ago
Convex delay models for transistor sizing
This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presente...
Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapat...
CODES
2004
IEEE
13 years 9 months ago
Analytical models for leakage power estimation of memory array structures
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
ISQED
2008
IEEE
98views Hardware» more  ISQED 2008»
13 years 11 months ago
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)
We proposed a combined magnetic and circuit level technique to explore the design methodology of SpinTorque Transfer RAM (SPRAM). A dynamic magnetic model of magnetic tunneling ju...
Yiran Chen, Xiaobin Wang, Hai Li, Harry Liu, Dimit...