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» Design of Testable Random Bit Generators
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CHES
2005
Springer
170views Cryptology» more  CHES 2005»
10 years 8 months ago
Design of Testable Random Bit Generators
Abstract. In this paper, the evaluation of random bit generators for security applications is discussed and the concept of stateless generator is introduced. It is shown how, for t...
Marco Bucci, Raimondo Luzzi
ITC
1994
IEEE
151views Hardware» more  ITC 1994»
10 years 6 months ago
Automated Logic Synthesis of Random-Pattern-Testable Circuits
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
Nur A. Touba, Edward J. McCluskey
IJNSEC
2010
98views more  IJNSEC 2010»
9 years 9 months ago
A Random Bit Generator Using Chaotic Maps
Chaotic systems have many interesting features such as sensitivity on initial condition and system parameter, ergodicity and mixing properties. In this paper, we exploit these int...
Narendra K. Pareek, Vinod Patidar, Krishan K. Sud
FPGA
2004
ACM
234views FPGA» more  FPGA 2004»
10 years 6 months ago
An embedded true random number generator for FPGAs
Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had le...
Paul Kohlbrenner, Kris Gaj
ISSTA
2004
ACM
10 years 8 months ago
Evolutionary testing in the presence of loop-assigned flags: a testability transformation approach
Evolutionary testing is an effective technique for automatically generating good quality test data. However, for structural testing, the technique degenerates to random testing i...
André Baresel, David Binkley, Mark Harman, ...
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