195 search results - page 3 / 39 » Design of clocked circuits using UML |
DATE
2009
IEEE
14 years 16 days ago
2009
IEEE
—In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthe...
DAC
2003
ACM
13 years 11 months ago
2003
ACM
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
ISCAS
2008
IEEE
14 years 6 days ago
2008
IEEE
—A simple low-area and low-power clock frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. In this circuit, 2n voltage controlled delay lines (...
ICCD
2001
IEEE
14 years 2 months ago
2001
IEEE
Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...