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DATE
2009
IEEE

Register placement for high-performance circuits

9 years 6 months ago
Register placement for high-performance circuits
—In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthesis (CTS) for local clock optimization are used so far, but new methodologies are necessary as the technology node advances. In this paper, we study the register placement problem which is a key component of local clock optimization for highperformance circuit design along with local clock distribution. We formulate it as a minimum weighted maximum independent set problem on a weighted conflict graph and propose a novel efficient two-stage heuristic to solve it. To reduce the graph size, techniques based on register flipping and Manhattan circle are also presented. Experiments show that our heuristic can place all registers without overlaps and achieve significant improvement on the total and maximal register movement.
Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura
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