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» Design optimizations for microprocessors at low temperature
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ICCD
2001
IEEE
106views Hardware» more  ICCD 2001»
14 years 2 months ago
A Low-Power Cache Design for CalmRISCTM-Based Systems
Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dom...
Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woo...
ISCAS
2005
IEEE
147views Hardware» more  ISCAS 2005»
13 years 11 months ago
A two-chip, 4-MHz, microelectromechanical reference oscillator
— The paper describes a 4-MHz temperature compensated reference oscillator based on a capacitive silicon micro-mechanical resonator. The design of the resonator has been optimize...
Krishnakumar Sundaresan, Paul S. Ho, Siavash Pourk...
VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
14 years 6 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood
DAC
2009
ACM
14 years 17 days ago
Throughput optimal task allocation under thermal constraints for multi-core processors
It is known that temperature gradients and thermal hotspots affect the reliability of microprocessors. Temperature is also an important constraint when maximizing the performance...
Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrud...
GLVLSI
2006
IEEE
185views VLSI» more  GLVLSI 2006»
13 years 12 months ago
Application of fast SOCP based statistical sizing in the microprocessor design flow
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
Murari Mani, Mahesh Sharma, Michael Orshansky