84 search results - page 1 / 17 » Designing and testing fault-tolerant techniques for SRAM-bas... |
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
CF
2004
ACM
13 years 10 months ago
2004
ACM
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
FPL
2001
Springer
13 years 9 months ago
2001
Springer
Designers of safety-critical VLSI systems are asking for effective tools for evaluating and validating their designs. Fault Injection is commonly adopted for this task, and its eff...
DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
– The implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for dupl...