139 search results - page 3 / 28 » Distributed sleep transistor network for power reduction |
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
— Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the sleep transistor which is used to...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
— Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells in standby mode reduces the leakage curren...
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...
VLSI
2005
Springer
13 years 11 months ago
2005
Springer
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...
HPCA
2005
IEEE
14 years 5 months ago
2005
IEEE
If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption in high performance processors. Caches, due to the f...