55 search results - page 2 / 11 » Double-via-driven standard cell library design |
DAC
1997
ACM
13 years 9 months ago
1997
ACM
This paper describes a fully automatic standard-cell layout synthesis system, CELLERITY. The system is flexible in supporting a wide variety of process technologies and a range of...
ASPDAC
2000
ACM
13 years 10 months ago
2000
ACM
Two compact yet high performance standard cell libraries (CyHP libraries), which contain only 11111111 and 20 cells respectively, are proposed. The first CyHP library leads to 5% i...
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
Design for Manufacturability (DFM) is becoming increasingly important as process geometries shrink. Conventional design rule pass/fail is not adequate to quantify DFM compliance. ...
ISVLSI
2008
IEEE
14 years 1 hour ago
2008
IEEE
A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-...
GLVLSI
1997
IEEE
13 years 9 months ago
1997
IEEE
In a VHDL-based design flow for applicationspecific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Sta...