473 search results - page 1 / 95 » Dynamic Flip-Flop with Improved Power |
ICCD
2000
IEEE
14 years 1 months ago
2000
IEEE
An improved design of a dynamic Flip-Flop is presented. Proposed design overcomes the problem of the glitch at the output and improves Power-Delay Product for about 10%, while pre...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
In this paper, a new flip-flop called Double-edge triggered Feedback Flip-Flop (DFFF) is proposed. The dynamic power consumption of DFFF is reduced by avoiding unnecessary interna...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper, we study the full-chp interconnect power modeling. ,We show that repeater,insertion is no longer sufficient to achievethe targetfrequencies specifiedhy ITRS, and de...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
The deep submicron (DSM) semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions sho...
ASPDAC
2000
ACM
13 years 9 months ago
2000
ACM
– This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master cloc...