13 search results - page 2 / 3 » Dynamic loop pipelining in data-driven architectures |
HPCA
2004
IEEE
14 years 5 months ago
2004
IEEE
This paper focuses on generating efficient software pipelined schedules for in-order machines, which we call Converged Trace Schedules. For a candidate loop, we form a string of t...
ISSS
1995
IEEE
13 years 8 months ago
1995
IEEE
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
CASES
2007
ACM
13 years 7 months ago
2007
ACM
Aggressive compiler optimizations such as software pipelining and loop invariant code motion can significantly improve application performance, but these transformations often re...
DATE
2009
IEEE
14 years 10 hour ago
2009
IEEE
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
MICRO
1998
IEEE
13 years 9 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...