35 search results - page 1 / 7 » Dynamically reconfigurable cache architecture using adaptive... |
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper, we present a dynamically reconfigurable cache architecture using adaptive block allocation policy analyzed by means of simulation. Our main objectives are: to propo...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
ISPASS
2008
IEEE
13 years 11 months ago
2008
IEEE
Many programs go through phases as they execute. Knowing where these phases begin and end can be beneficial. For example, adaptive architectures can exploit such information to lo...
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uni...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
Leakage power reduction in cache memories continues to be a critical area of research because of the promise of a significant pay-off. Various techniques have been developed so fa...