56 search results - page 3 / 12 » Efficient Backtracking Instruction Schedulers |
DAC
1995
ACM
13 years 9 months ago
1995
ACM
Application domain specific DSP cores are becoming increasingly popular due to their advantageous trade–off between flexibility and cost. However, existing code generation metho...
ICCD
2003
IEEE
14 years 2 months ago
2003
IEEE
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...
ASPLOS
1992
ACM
13 years 10 months ago
1992
ACM
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
HPCA
2004
IEEE
14 years 6 months ago
2004
IEEE
This paper focuses on generating efficient software pipelined schedules for in-order machines, which we call Converged Trace Schedules. For a candidate loop, we form a string of t...
MICRO
2010
IEEE
13 years 3 months ago
2010
IEEE
Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scien...