544 search results - page 1 / 109 » Efficient checker processor design |
MICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
The design and implementation of a modern microprocessor creates many reliability challenges. Designers must verify the correctness of large complex systems and construct implemen...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
MICRO
1999
IEEE
13 years 9 months ago
1999
IEEE
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
—Bus-based system-on-chip (SoC) design becomes the major integration methods for shorting design cycle and time-tomarket, thus how to verify IP functionality on bus protocol is a...