8 search results - page 1 / 2 » Efficient compression and application of deterministic patte... |
DAC
2003
ACM
13 years 9 months ago
2003
ACM
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for...
ET
2002
13 years 4 months ago
2002
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional co...
ETS
2006
IEEE
13 years 10 months ago
2006
IEEE
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
VTS
2005
IEEE
13 years 10 months ago
2005
IEEE
A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an ...