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» Efficient hardware code generation for FPGAs
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ARC
2010
Springer
183views Hardware» more  ARC 2010»
13 years 5 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
DATE
2005
IEEE
187views Hardware» more  DATE 2005»
13 years 10 months ago
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs will be presented. This translator generates code to run on a rapid prototyping ...
Jürgen Schnerr, Oliver Bringmann, Wolfgang Ro...
DATE
2009
IEEE
176views Hardware» more  DATE 2009»
13 years 11 months ago
Automated synthesis of streaming C applications to process networks in hardware
Abstract—The demand for embedded computing power is continuously increasing and FPGAs are becoming very interesting computing platforms, as they provide huge amounts of customiza...
Sven van Haastregt, Bart Kienhuis
FPL
2006
Springer
95views Hardware» more  FPL 2006»
13 years 8 months ago
Automation of IP Core Interface Generation for Reconfigurable Computing
Pre-designed IP cores for FPGAs represent a huge intellectual and financial wealth that must be leveraged by any high-level tool targeting reconfigurable platforms. In this paper ...
Zhi Guo, Abhishek Mitra, Walid A. Najjar
FPL
2008
Springer
150views Hardware» more  FPL 2008»
13 years 6 months ago
Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs
Wavefront algorithms, such as the Smith-Waterman algorithm, are commonly used in bioinformatics for exact local and global sequence alignment. These algorithms are highly computat...
Betul Buyukkurt, Walid A. Najjar