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» Efficient simulation of critical synchronous dataflow graphs
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ISSS
2000
IEEE
144views Hardware» more  ISSS 2000»
13 years 9 months ago
Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...
Hyunuk Jung, Kangnyoung Lee, Soonhoi Ha
RSP
1999
IEEE
125views Control Systems» more  RSP 1999»
13 years 9 months ago
Extended Synchronous Dataflow for Efficient DSP System Prototyping
Though synchronous dataflow (SDF) graph has been a successful input specification language for digital signal processing (DSP) applications, lack of support for global states makes...
Chanik Park, JaeWoong Chung, Soonhoi Ha
DAC
2009
ACM
13 years 8 months ago
Reduction techniques for synchronous dataflow graphs
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
Marc Geilen
DAC
2005
ACM
14 years 5 months ago
Minimising buffer requirements of synchronous dataflow graphs with model checking
Signal processing and multimedia applications are often implemented on resource constrained embedded systems. It is therefore important to find implementations that use as little ...
Marc Geilen, Twan Basten, Sander Stuijk
DAC
2007
ACM
14 years 5 months ago
Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs
Abstract. Embedded multimedia systems often run multiple time-constrained applications simultaneously. These systems use multiprocessor systems-on-chip of which it must be guarante...
Sander Stuijk, Twan Basten, Marc Geilen, Henk Corp...