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» Energy Recovering ASIC Design
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ISVLSI
2003
IEEE
103views VLSI» more  ISVLSI 2003»
13 years 10 months ago
Energy Recovering ASIC Design
Abstract— Dissipation in the clock tree and state elements of ASIC designs is often a significant fraction of total energy consumption. We propose a methodology for recovering m...
Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthy...
ISLPED
2004
ACM
149views Hardware» more  ISLPED 2004»
13 years 10 months ago
Creating a power-aware structured ASIC
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectur...
R. Reed Taylor, Herman Schmit
DAC
2005
ACM
13 years 7 months ago
Closing the power gap between ASIC and custom: an ASIC perspective
We investigate differences in power between application-specific integrated circuits (ASICs) and custom integrated circuits, with examples from 0.6um to 0.13um CMOS. A variety of ...
David G. Chinnery, Kurt Keutzer
DAC
2004
ACM
13 years 8 months ago
Enabling energy efficiency in via-patterned gate array devices
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architecture...
R. Reed Taylor, Herman Schmit
CDES
2006
158views Hardware» more  CDES 2006»
13 years 6 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia