23 search results - page 2 / 5 » Energy and latency evaluation of NoC topologies |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
VLSI
2005
Springer
13 years 10 months ago
2005
Springer
This work addresses the problem of application mapping in networks-on-chip (NoCs) having as goal to minimize the total dynamic energy consumption of a complex system-on-a-chip (So...
DATE
2004
IEEE
13 years 9 months ago
2004
IEEE
A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency an...