18 search results - page 1 / 4 » Energy recovery clocked dynamic logic |
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
Energy recovery clocking results in significant energy savings in clock distribution networks as compared to conventional squarewave clocking. However, since energy recovery clock...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
FSKD
2005
Springer
13 years 10 months ago
2005
Springer
Core operations (e.g. TDMA scheduler, synchronized sleep period, data aggregation) of many proposed protocols for different layer of sensor network necessitate clock synchronizatio...
MJ
2008
13 years 4 months ago
2008
Circuits optimized for minimum energy consumption operate typically in the subthreshold regime with ultra-low power-supply voltages. Speed of a subthreshold logic circuit is enhan...
OSDI
1994
ACM
13 years 6 months ago
1994
ACM
The energy usage of computer systems is becoming more important, especially for battery operated systems. Displays, disks, and cpus, in that order, use the most energy. Reducing t...