21 search results - page 1 / 5 » Evaluating ASIC, DSP, and RISC Architectures for Embedded Ap... |
IPPS
1998
IEEE
13 years 9 months ago
1998
IEEE
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but al...
CSREAESA
2006
13 years 6 months ago
2006
- This paper presents a dual-core embedded System-on-Chip for a wide range of application fields with particularly high processing demands, including general signal processing, vid...
SAC
2004
ACM
13 years 10 months ago
2004
ACM
High mask and production costs for the newest CMOS silicon technologies increase the pressure to develop hardware platforms useable for different applications or variants of the s...
ISCAPDCS
2001
13 years 6 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...