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MICRO
1997
IEEE
90views Hardware» more  MICRO 1997»
13 years 9 months ago
ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors
Profile data is valuable for identifying performance bottlenecks and guiding optimizations. Periodic sampling of a processor's performance monitoring hardware is an effective...
Jeffrey Dean, James E. Hicks, Carl A. Waldspurger,...
ASAP
2007
IEEE
118views Hardware» more  ASAP 2007»
13 years 7 months ago
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
Götz Kappen, S. el Bahri, O. Priebe, Tobias G...
IPPS
2005
IEEE
13 years 11 months ago
Analysis of Hardware Acceleration in Reconfigurable Embedded Systems
Embedded designers now have the capability of offloading software routines into custom applicationspecific hardware blocks. This paper evaluates a domain-specific design system fo...
Matthew Ouellette, Daniel A. Connors
CASES
2008
ACM
13 years 7 months ago
VESPA: portable, scalable, and flexible FPGA-based vector processors
While soft processors are increasingly common in FPGAbased embedded systems, it remains a challenge to scale their performance. We propose extending soft processor instruction set...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
MICRO
2007
IEEE
159views Hardware» more  MICRO 2007»
13 years 11 months ago
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation
As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common. Such defects are bound to hinder the correct operation of future ...
Kypros Constantinides, Onur Mutlu, Todd M. Austin,...