201 search results - page 2 / 41 » Evaluating Run-Time Techniques for Leakage Power Reduction |
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
As frequencies and feature size scale faster than operating voltages, power density is increasing in each processor generation. Power density and the cost of removing the heat it ...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
— Security is emerging as an important concern in embedded system design. The security of embedded systems is often compromised due to vulnerabilities in “trusted” software t...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, two packing algorithms for the detection of activity profiles in MTCMOS-based FPGA structures are proposed for leakage power mitigation. The first algorithm is a ...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...
TCAD
2008
13 years 5 months ago
2008
Three-dimensional integration has the potential to improve the communication latency and integration density of chip-level multiprocessors (CMPs). However, the stacked highpower de...