40 search results - page 2 / 8 » Evaluation of a High-Level-Language Methodology for High-Per... |
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
HPCA
2003
IEEE
14 years 5 months ago
2003
IEEE
Increasing focus on power dissipation issues in current microprocessors has led to a host of proposals for clock gating and other power-saving techniques. While generally effectiv...
IPPS
2005
IEEE
13 years 11 months ago
2005
IEEE
Reconfigurable computing offers the promise of performing computations in hardware to increase performance and efficiency while retaining much of the flexibility of a software sol...
TIM
2010
13 years 6 days ago
2010
Abstract--The most popular representative devices of reconfigurable computing are the Field Programmable Gate Arrays (FPGAs). A promising feature of an FPGA is the ability to reuse...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper, we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict topdown Hardware/So...