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DATE
2005
IEEE
154views Hardware» more  DATE 2005»
13 years 10 months ago
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi,...
DSD
2006
IEEE
183views Hardware» more  DSD 2006»
13 years 11 months ago
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption h...
Panu Hämäläinen, Timo Alho, Marko H...
DAC
2000
ACM
14 years 5 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf
APCCAS
2006
IEEE
256views Hardware» more  APCCAS 2006»
13 years 11 months ago
Asynchronous Design Methodology for an Efficient Implementation of Low power ALU
— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...
P. Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, ...