290 search results - page 2 / 58 » Exploiting Temporal Uncertainty in Parallel and Distributed ... |
IPPS
2010
IEEE
13 years 3 months ago
2010
IEEE
Multi-core organizations increasingly support multiple threads per core. Threads on a core usually share a single first-level data cache, so thread schedulers must try to minimize ...
ICPP
2009
IEEE
14 years 6 days ago
2009
IEEE
Parallel simulation is a technique to accelerate microarchitecture simulation of CMPs by exploiting the inherent parallelism of CMPs. In this paper, we explore the simulation para...
PADS
2004
ACM
13 years 11 months ago
2004
ACM
We investigated the benefit of exploiting the symmetries of graphs for partitioning. We represent the model to be simulated by a weighted graph. Graph symmetries are studied in th...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
FPGA chips in reconfigurable computer systems are used as malleable coprocessors where components of a hardware library of functions can be configured as needed. As the number of ...
EURODAC
1995
IEEE
13 years 9 months ago
1995
IEEE
This paper describes VHDL compilation techniques, embodied in the Auriga compiler [3,14], which facilitate parallel or distributed simulation by embedding evaluation scheduling in...