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» Exploring Area Delay Tradeoffs in an AES FPGA Implementation
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FPL
2004
Springer
143views Hardware» more  FPL 2004»
13 years 8 months ago
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation
Abstract. Field-Programmable Gate Arrays (FPGAs) have lately become a popular target for implementing cryptographic block ciphers, as a well-designed FPGA solution can combine some...
Joseph Zambreno, David Nguyen, Alok N. Choudhary
DAC
2001
ACM
14 years 5 months ago
Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers
: Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concu...
Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook K...
CHES
2003
Springer
146views Cryptology» more  CHES 2003»
13 years 8 months ago
Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs
Abstract. Performance evaluation of the Advanced Encryption Standard candidates has led to intensive study of both hardware and software implementations. However, although plentifu...
François-Xavier Standaert, Gaël Rouvro...
CCS
2007
ACM
13 years 10 months ago
Compact FPGA implementations of QUAD
QUAD is a stream cipher whose provable security relies on the hardness of solving systems of multivariate quadratic equations. This paper explores FPGA implementations of the stre...
David Arditti, Côme Berbain, Olivier Billet,...
TVLSI
2010
12 years 11 months ago
Design and Implementation of a Sort-Free K-Best Sphere Decoder
:- This paper describes the design and VLSI architecture for a 4x4 breadth first K-Best MIMO decoder using a 64 QAM scheme. A novel sort free approach to path extension, as well as...
Sudip Mondal, Ahmed M. Eltawil, Chung-An Shen, Kha...