29 search results - page 4 / 6 » Exploring SW Performance Using SoC Transaction-Level Modelin... |
ASPDAC
2009
ACM
14 years 15 days ago
2009
ACM
Abstract— This paper presents synthesis of Hardware Dependent Software (HdS) for multicore and many-core designs using Embedded System Environment (ESE). ESE is a tool set, devel...
ASPDAC
2006
ACM
13 years 12 months ago
2006
ACM
- Early estimation of the execution time of Real-Time embedded SW is an essential task in complex, HW/SW embedded system design. Application SW execution time estimation requires t...
LCTRTS
2010
Springer
14 years 25 days ago
2010
Springer
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
FDL
2007
IEEE
14 years 10 days ago
2007
IEEE
Transaction level models (TLMs) can be constructed at t levels of abstraction, denoted as untimed (UT), cycle-approximate (CX), and cycle accurate (CA) in this paper. The choice o...
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
System-on-chip (SoC) designs use bus protocols for high performance data transfer among the Intellectual Property (IP) cores. These protocols incorporate advanced features such as...