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ERSA
2003
139views Hardware» more  ERSA 2003»
13 years 7 months ago
Fast Design Space Exploration Method for Reconfigurable Architectures
In this paper we propose an original and fast design space exploration method targeting reconfigurable architectures. This method takes place during the first steps of a design fl...
Lilian Bossuet, Guy Gogniat, Jean Luc Philippe
RTCSA
2007
IEEE
14 years 2 days ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
LCTRTS
2010
Springer
14 years 18 days ago
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
Ines Viskic, Lochi Lo Chi Yu Lo, Daniel Gajski
DSD
2009
IEEE
124views Hardware» more  DSD 2009»
14 years 16 days ago
Network-on-Chip Architecture Exploration Framework
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...
Timo Schönwald, Jochen Zimmermann, Oliver Bri...
FDL
2007
IEEE
14 years 4 days ago
Mapping Actor-Oriented Models to TLM Architectures
Actor-oriented modeling approaches are convenient for implementing functional models of embedded systems. Architectural models for heterogeneous system-on-chip architectures, howe...
Jens Gladigau, Christian Haubelt, Bernhard Niemann...