22 search results - page 2 / 5 » FPGA Interconnect Delay Fault Testing |
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
— Fault diagnosis has particular importance in the context of field programmable gate arrays (FPGAs) because faults can be avoided by reconfiguration at almost no real cost. Cl...
DSD
2006
IEEE
13 years 11 months ago
2006
IEEE
Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when th...
ITC
1998
IEEE
13 years 9 months ago
1998
IEEE
: We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affect...
FPGA
2006
ACM
13 years 8 months ago
2006
ACM
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
－ We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and cr...